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FEATURES ADV478/ADV471 (ADV(R)) Register Level Compatible IBM PS/2,* VGA*/XGA* Compatible 135 MHz Pipelined Operation Triple 8-Bit D/A Converters Triple 256 8 (256 24) Color Palette RAM Three 15 8 Overlay Registers On-Board Voltage Reference RS-343A/RS-170 Compatible Analog Outputs TTL Compatible Digital Inputs and Outputs Sync on All Three Channels Programmable Pedestal (0 or 7.5 IRE) Standard MPU l/O Interface +5 V CMOS Monolithic Construction 68-Pin PLCC Package APPLICATIONS High Resolution Color Graphics True-Color Visualization CAE/CAD/CAM Image Processing Desktop Publishing
CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DAC ADV473
MODES 24-Bit True Color 8-Bit Pseudo Color 15-Bit True Color 8-Bit True Color SPEED GRADES 135 MHz, 110 MHz 80 MHz, 66 MHz GENERAL DESCRIPTION
The ADV473 is a complete analog output, Video RAM-DAC on a single CMOS monolithic chip. The part is specifically designed for true-color computer graphics systems. The ADV473 integrates a number of graphic functions onto one device allowing 24-bit direct true-color operation at the maximum screen update rate of 135 MHz. It can also be used in other modes, including 15-bit true color and 8-bit pseudo or indexed color. The ADV473 is fully PS/2 and VGA register level compatible. It is also capable of implementing IBM's XGA standard. (Continued on page 4)
FUNCTIONAL BLOCK DIAGRAM
VREFIN SYNC BLANK S0 S1 VREFOUT
VOLTAGE REFERENCE GENERATOR
OL0 OVERLAYS OL3
4
P I X E L P O R T
OVERLAY PALETTE 15 x 8 RAM 15 x 8 RAM 15 x 8 RAM 8 8 8 COLOR PALETTE
8 8 8 VOLTAGE REFERENCE CONTROL CIRCUIT COLOR PALETTE/ OVERLAY PALETTE SWITCHER
OPA
RED
R0 R7 G0 G7
8
8
GREEN
8
8
SWITCHING MATRIX & PIXEL MASK
8 8
RED 256 x 8 RAM
8
8
D A C P O R T
8
RED DAC GREEN DAC BLUE DAC
IOR
GREEN 256 x 8 RAM BLUE 256 x 8 RAM
8
8
8
IOG
BLUE
B0 B7
8
8
8
8
8
8
IOB
CLOCK 8 MODE CONTROL REGISTERS PIXEL MASK REGISTERS RED REG 8 GREEN REG MPU PORT 8 8 BLUE REG ADDRESS REG MPU & PIXEL PORT CONTROL LOGIC CR0 CR1 CR2 CR3
ADV473
D0-D7
RD
WR
RS0 RS1
RS2
ADV is a registered trademark of Analog Devices Inc. *Personal System/2 and VGA are trademarks of International Business Machines Corp.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
ADV473-SPECIFICATIONS
Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity Gray Scale Error Coding DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Leakage Capacitance ANALOG OUTPUTS Gray Scale Current Range Output Current White Level Relative to Black Black Level Relative to Blank (Pedestal = 7.5 IRE) Black Level Relative to Blank (Pedestal = 0 IRE) Blank Level Sync Level LSB Size DAC-to-DAC Matching Output Compliance, VOC Output Capacitance, COUT Output Impedance, ROUT VOLTAGE REFERENCE Internal Voltage Reference (VREFOUT) External Voltage Reference Range Input Current, IVREF (Internal Reference) Input Current (External Reference) POWER SUPPLY Supply Voltage, VAA Supply Current, IAA3 2 0.8 1 7 2.4 0.4 50 7 20 8
(VAA1 = 5 V; VREF = 1.235 V; RL = 37.5 , CL = 10 pF; RSET = 140 . All specifications TMIN to TMAX2 unless otherwise noted.)
Units Bits LSB max LSB max % Gray Scale % Gray Scale Binary V min V max A max pF max V min V max A max pF max mA max mA min mA max mA min mA max A min A max mA min mA max A min A max A typ % max V min V max pF max k typ V min/V max V min/V max A typ A typ V min/V max mA max mA max mA max mA max dB typ pV secs typ dB typ Typically 17.62 mA Typically 1.44 mA Typically 5 A Typically 7.62 mA Typically 5 A Test Conditions/Comments
All Versions
1 1 5 10
Guaranteed Monotonic External Reference Internal Reference
VIN = 0.4 V or 2.4 V f = 1 MHz, VIN = 2.4 V ISOURCE = 400 A ISINK = 3.2 mA
16.74 18.50 0.95 1.90 0 50 6.29 8.96 0 50 69.1 2 0 +1.5 30 10 1.08/1.32 1.14/1.26 100 10 4.75/5.25 400 300 250 200 -30 75 -23
Typically 1%
f = 1 MHz, IOUT = 0 mA
Typically 1.235 V Typically 1.235 V
135 MHz Parts 110 MHz Parts 80 MHz Parts 66 MHz Parts
DYNAMIC PERFORMANCE Clock and Data Feedthrough4, 5 Glitch Impulse4, 5 DAC-to-DAC Crosstalk6
NOTES 1 VAA = 5 V 5% 2 Temperature range (TMIN to TMAX); 0C to +70C; TJ (Silicon Junction Temperature) 100C. 3 Pixel Port is continuously clocked with data corresponding to a linear ramp. 4 Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough. 5 TTL input values are 0 to 3 volts, with input rise/fall times 3 ns, measured at the 10% and 90% points. Timing reference points at 50% for inputs and outputs. 6 DAC to DAC Crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions. Specifications subject to change without notice.
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REV. A
ADV473 TIMING
Parameter fmax t1 t2 t3 4 t4 4 t5 5 t6 5 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t196 tSK tPD
AA REF L L SET CHARACTERISTICS1 All specifications TMIN to TMAX3 unless otherwise noted.)
(V
2
= 5 V; V
= 1.235 V; R = 37.5 , C = 10 pF; R
66 MHz Version 66 10 10 3 40 20 5 10 10 100 50 40 3 3 15.15 5 5 30 3 13 2 4 x t14
= 140 .
135 MHz Version 135 10 10 3 40 20 5 10 10 100 50 40 2 2 7.4 3 2 30 3 13 2 4 x t14
110 MHz Version 110 10 10 3 40 20 5 10 10 100 50 40 3 3 9.1 3.5 3 30 3 13 2 4 x t14
80 MHz Version 80 10 10 3 40 20 5 10 10 100 50 40 3 3 12.5 4 4 30 3 13 2 4 x t14
Units MHz ns min ns min ns min ns max ns max ns min ns min ns min ns max ns min ns min ns min ns min ns min ns min ns min ns max ns typ ns max ns max ns
Conditions/Comments Clock Rate RS0-RS2 Setup Time RS0-RS2 Hold Time RD Asserted to Data Bus Driven RD Asserted to Data Valid RD Negated to Data Bus 3-Stated Read Data Hold Time Write Data Setup Time Write Data Hold Time CR0-CR3 Delay Time RD, WR Pulse Width Low RD, WR Pulse Width High Pixel & Control Setup Time Pixel & Control Hold Time Clock Cycle Time Clock Pulse Width High Time Clock Pulse Width Low Time Analog Output Delay Analog Output Rise/Fall Time Analog Output Settling Time Analog Output Skew Pipeline Delay
NOTES 1 TTL input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load 10 pF, D0-D7 output load 50 pF. See timing notes in Figure 2. 2 VAA = 5 V 5%. 3 Temperature range (T MIN to TMAX); 0C to +70C; TJ (Silicon Junction Temperature) 100C . 4 t3 and t4 are measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.4 V or 2.4 V. 5 t5 and t6 are derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging the 50 pF capacitor. This means that the times, t 5 and t6, quoted in the timing characteristics are the true values for the device and, as such, are independent of external bus loading capacitances. 6 Settling time does not include clock and data feedthrough. Specifications subject to change without notice.
t14 t16
3.2mA
DATA
t1
RS0, RS1, RS2 RD, WR
VALID
t2
CLOCK
t15
t10 t4 t3
DATA OUT (RD = 0)
t11 t5 t6
R0-R7, G0-G7, B0-B7, OL0-OL3, S0-S1, SYNC, BLANK IOR, IOG, IOB
t12 t13
t17
D0-D7 (READ) D0-D7 (WRITE)
t19
TO OUTPUT PIN 50pF 400A
+2.1V
DATA IN (WR = 0)
t7
CR0-CR3
t8 t9
t18 NOTES 1. OUTPUT DELAY MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION. 2. SETTLING TIME MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO THE OUTPUT REMAINING WITHIN 1 LSB. 3. OUTPUT RISE/FALL TIME MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.
Figure 1. MPU Read/Write Timing
Figure 2. Video Input/Output Timing
Figure 3. Load Circuit for Bus Access and Relinquish Time
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ADV473 RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Ambient Operating Temperature Output Load Reference Voltage
ABSOLUTE MAXIMUM RATINGS 1
Symbol VAA TA RL VREF
Min 4.75 0 1.14
Typ 5.00 37.5 1.235
Max 5.25 +70 1.26
Units Volts C Volts
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage on Any Digital Pin . . . . GND - 0.5 V to VAA + 0.5 V Ambient Operating Temperature (TA) . . . . . -55C to +125C Storage Temperature (TS) . . . . . . . . . . . . . . -65C to +150C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . +150C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300C Vapor Phase Soldering (2 minutes) . . . . . . . . . . . . . . +220C IOR, IOG, IOB to GND2 . . . . . . . . . . . . . GND-0.5 V to VAA
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Analog output short circuit to any power supply or common can be of an indefinite duration.
PIN CONFIGURATION 68-Pin PLCC
CLOCK SYNC BLANK GND GND VAA VAA
B4
B3
B7
B6
9
8
SI
S0
B5
B1
7
6
5
4
3
2
1
68
67
66
65
64
63
62
B2
61 60 59 58 57 56 55 54 53
B0
OL0 OL1 OL2 OL3 D0 D1 D2 D3 D4 D5 D6 D7 WR
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
G7 G6 G5 G4 G3 G2 G1 G0 R7 R6 R5 R4 R3 R2 R1 R0 VREFOUT
ADV473
TOP VIEW (Not To Scale)
52 51 50 49 48 47 46 45 44
ORDERING GUIDE
Model ADV473KP135 ADV473KP110 ADV473KP80 ADV473KP66
Speed 135 MHz 110 MHz 80 MHz 66 MHz
Temperature No. of Package Range Pins Option* 0C to +70C 0C to +70C 0C to +70C 0C to +70C 68 68 68 68 P-68A P-68A P-68A P-68A
RD RS0 RS1 RS2
CR1
GND
GND
CR0
CR2
IOG
IOB
COMP
COMP
CR3
VAA
VAA
VAA
IOR
NOTE * All devices are packaged in a 68-pin plastic leaded (J-lead) chip carrier.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV473 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
(Continued from page 1) The device consists of three, high speed, 8-bit, video D/A converters (RGB), a 256 24 RAM which can be configured as a look-up table or a linearization RAM, a 24-bit wide parallel pixel input port and three 15 8 overlay registers. The part is controlled through the MPU port by the various on-board control/command registers. The individual red, green and blue pixel input ports allow truecolor, image rendition. True-color image rendition, at speeds of up to 135 MHz, is achieved through the 24-bit pixel input port. The ADV473 is also capable of implementing 8-bit true color, 8-bit pseudo color and 15-bit true color. The ADV473 is capable of generating RGB video output signals, without requiring external buffering, and which are compatible with RS-343A and RS-170 video standards. All digital inputs and outputs are TTL compatible. The part can be driven by the on-board voltage reference or an external voltage reference. The part is packaged in a 68-pin Plastic Leaded Chip Carrier (PLCC).
VREFIN
VAA
RSET
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ADV473
PIN FUNCTION DESCRIPTION BLANK Composite Blank Control Input (TTL Compatible). A logic zero drives the analog outputs to the blanking level. It is latched on the rising edge of CLOCK. When BLANK is a logical zero, the pixel and overlay inputs are ignored. Composite SYNC Control Input (TTL Compatible). A logical zero on this input switches off a 40 IRE current source on the analog outputs. SYNC does not override any other control or data input; therefore, it should be asserted only during the blanking interval. It is latched on the rising edge of CLOCK. If sync information is not required on the analog outputs, SYNC should be connected to ground. Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0-R7, G0-G7, B0-B7, S0, S1, OL0-OL3, SYNC, and BLANK inputs. It is typically the pixel clock rate of the video system. It is recommended that CLOCK be driven by a dedicated TTL buffer. Red, Green and Blue Select Inputs (TTL Compatible). These inputs specify, on a pixel basis, the color value to be written to the DACs. They are latched on the rising edge of CLOCK. R0, G0 and B0 are the LSBs. Unused inputs should be connected to GND. Color Mode Select Inputs (TTL Compatible). These inputs specify the mode of operation as shown in Table III. They are latched on the rising edge of CLOCK. Overlay Select Inputs (TTL Compatible). These inputs specify which palette is to be used to provide color information. When accessing the overlay palette, the R0-R7, G0-G7, B0-B7, S0 and S1 inputs are ignored. They are latched on the rising edge of CLOCK. OL0 is the LSB. Unused inputs should be connected to GND. Red, Green, and Blue Current Outputs. These high impedance current sources are capable of directly driving a doubly terminated 75 coaxial cable. Full-Scale Adjust Resistor. A resistor (R SET) connected between this pin and GND controls the magnitude of the full-scale video signal. The relationship between R SET and the full-scale output current on each output is: RSET () = 3,195 x VREF (V)/IOUT (mA) SETUP = 7.5 IRE) RSET () = 3,025 x VREF (V)/IOUT (mA) SETUP = 0 IRE) Compensation Pin. These pins should be connected together at the chip and connected through 0.1 F ceramic capacitor to VAA. Voltage Reference Input. This input requires a 1.2 V reference voltage. This is achieved through the on-board voltage reference generator by connecting V REFOUT to VREFIN. If an external reference is used, it must supply this input with a 1.2 V (typical) reference. Voltage Reference Output. This output delivers a 1.2 V reference voltage from the device's on-board voltage reference generator. It is normally connected directly to the V REFIN pin. If it is preferred to use an external voltage reference, this pin may be left floating. Up to four ADV473s can be driven from V REFOUT. Analog power. All VAA pins must be connected. Analog Ground. All GND pins must be connected. Write Control Input (TTL Compatible). D0-D7 data is latched on the rising edge of WR, and RS0-RS2 are latched on the falling edge of WR during MPU write operations. RD and WR should not be asserted simultaneously. Read Control Input (TTL Compatible). To read data from the device, RD must be a logical zero. RS0-RS2 are latched on the falling edge of RD during MPU read operations. RD and WR should not be asserted simultaneously. Register Select Inputs (TTL Compatible). RS0-RS2 specify the type of read or write operation being performed. Data Bus (TTL Compatible). Data is transferred into and out of the device over this eight-bit bidirectional data bus. D0 is the least significant bit. Control Outputs (TTL Compatible). These outputs are used to control application specific features. The output values are determined by the contents of the command register (CR).
SYNC
CLOCK
R0-R7 B0-B7 G0-G7 S0, S1 OL0-OL3
IOR, IOG, IOB RSET
COMP VREFIN
VREFOUT
VAA GND WR
RD
RS0, RS1, RS2 D0-D7 CR0-CR7
REV. A
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ADV473
TERMINOLOGY BLANKING LEVEL CIRCUIT DESCRIPTION MPU Interface
The level separating the SYNC portion from the video portion of the waveform. Usually referred to as the front porch or back porch. At 0 IRE units, it is the level which will shut off the picture tube, resulting in the blackest possible picture.
COLOR VIDEO (RGB)
The ADV473 supports a standard MPU bus interface, allowing the MPU direct access to the color palette RAM and overlay color registers. Three address decode lines, RS0-RS2, specify whether the MPU is accessing the address register, the color palette RAM, the overlay registers, or read mask register. These controls also determine whether this access is a read or write function. Table I illustrates this decoding. The 8-bit address register is used to address the contents of the color palette RAM and overlay registers.
Table I. Control Input Truth Table
This usually refers to the technique of combining the three primary colors of red, green and blue to produce color pictures within the usual spectrum. In RGB monitors, three DACs are required, one for each color.
COMPOSITE SYNC SIGNAL (SYNC)
The position of the composite video signal which synchronizes the scanning process.
COMPOSITE VIDEO SIGNAL
RS2 0 0 0 0 1 1 1 1
RS1 0 1 0 1 0 1 0 1
RS0 0 1 1 0 0 1 1 0
Addressed by MPU Address Register (RAM Write Mode) Address Register (RAM Read Mode) Color Palette RAM Pixel Read Mask Register Address Register (Overlay Write Mode) Address Register (Overlay Read Mode) Overlay Registers Command Register
The video signal with or without setup, plus the composite SYNC signal.
GRAY SCALE
The discrete levels of video signal between reference black and reference white levels. An 8-bit DAC contains 256 different levels while a 6-bit DAC contains 64.
RASTER SCAN
The most basic method of sweeping a CRT one line at a time to generate and to display images.
REFERENCE BLACK LEVEL
Color Palette Writes
The maximum negative polarity amplitude of the video signal.
REFERENCE WHITE LEVEL
The maximum positive polarity amplitude of the video signal.
SETUP
The difference between the reference black level and the blanking level.
SYNC LEVEL
The peak level of the composite SYNC signal.
VIDEO SIGNAL
That portion of the composite video signal which varies in gray scale levels between reference white and reference black. Also referred to as the picture signal, this is the portion which may be visually observed.
The MPU writes to the address register (selecting RAM write mode, RS2 = 0, RS1 = 0 and RS0 = 0) with the address of the color palette RAM location to be modified. The MPU performs three successive write cycles (8 or 6 bits each of red, green, and blue), using RS0-RS2 to select the color palette RAM (RS2 = 0, RS1 = 0, RS0 = 1). After the BLUE write cycle, the three bytes of color information are concatenated into a 24-bit word or an 18-bit word and written to the location specified by the address register. The address register then increments to the next location which the MPU may modify by simply writing another sequence of red, green, and blue data. A complete set of colors can be loaded into the palette by initially writing the start address and then performing a sequence of RED, GREEN and BLUE writes. The address automatically increments to the next highest location after a BLUE write.
Color Palette Reads
The MPU writes to the address register (selecting RAM read mode, RS2 = 0, RS1 = 1 and RS0 = 1) with the address of the color palette RAM location to be read back. The contents of the palette RAM are copied to the RED, GREEN and BLUE registers and the address register increments to point to the next palette RAM location. The MPU then performs three successive read cycles (8 or 6 bits each of red, green, and blue), using RS0-RS2 to select the color palette RAM (RS2 = 0, RS1 = 0, RS0 = 1). After the BLUE read cycle, the 24/18 bit contents of the palette RAM at the location specified by the address register is loaded into the RED, GREEN and BLUE registers. The address register then increments to the next location which the MPU can read back by simply reading another sequence of red, green, and blue data. A complete set of colors can be read back from the palette by initially writing the start address and then performing a sequence of RED, GREEN and BLUE reads. The address automatically increments to the next highest location after a BLUE read. -6- REV. A
ADV473
Table II. Address Register (ADDR) Operation
Value ADDRa,b (Counts Modulo 3) 00 01 10 00H-FFH XXXX 0000 XXXX 0001 XXXX 0010 * * XXXX 1111
RS2 X X X 0 1 1 1 * * 1
RS1 0 0 0 0 0 0 0 * * 0
RS0 1 1 1 1 1 1 1 * * 1
Addressed by MPU Red Value Green Value Blue Value Color Palette RAM Reserved Overlay Color 1 Overlay Color 2 * * Overlay Color 15
ADDR0-7 (Counts Binary)
Overlay Color Writes
The MPU writes to the address register (selecting OVERLAY REGISTER write mode, RS2 = 1, RS1 = 0 and RS0 = 0) with the address of the overlay register to be modified. The MPU performs three successive write cycles (8 or 6 bits each of red, green, and blue), using RS0-RS2 to select the Overlay Registers (RS2 = 1, RS1 = 0, RS0 = 1). After the BLUE write cycle, the three bytes of color information are concatenated into a 24-bit word or an 18-bit word and are written to the overlay register specified by the address register. The address register then increments to the next overlay register which the MPU may modify by simply writing another sequence of red, green, and blue data. A complete set of colors can be loaded into the overlay registers by initially writing the start address and then performing a sequence of RED, GREEN and BLUE writes. The address automatically increments to the next highest location after a BLUE write.
Overlay Color Reads
However, while accessing the overlay color registers, the four most significant bits (since there are only 15 overlay registers) of the address register (ADDR4-7) are ignored. To keep track of the red, green, and blue read/write cycles, the address register has two additional bits (ADDRa, ADDRb) that count modulo three, as shown in Table II. They are reset to zero when the MPU writes to the address register, and are not reset to zero when the MPU reads the address register. The MPU does not have access to these bits. The other eight bits of the address register, incremented following a blue read or write cycle, (ADDR0-7) are accessible to the MPU, and are used to address color palette RAM locations and overlay registers, as shown in Table II. ADDR0 is the LSB when the MPU is accessing the RAM or overlay registers. The MPU may read the address register at any time without modifying its contents or the existing read/write mode.
Synchronization
The MPU writes to the address register (selecting OVERLAY REGISTER read mode, RS2 = 1, RS1 = 1 and RS0 = 1) with the address of the overlay register to be read back. The contents of the overlay register are copied to the RED, GREEN and BLUE registers and the address register increments to point to the next highest overlay register. The MPU then performs three successive read cycles (8 or 6 bits each of red, green, and blue), using RS0 - RS2 to select the Overlay Registers (RS2 = 1, RS1 = 0, RS0 = 1). After the BLUE read cycle, the 24/18 bit contents of the overlay register at the specified address register location is loaded into the RED, GREEN and BLUE registers. The address register then increments to the next overlay register which the MPU can read back by simply reading another sequence of red, green, and blue data. A complete set of colors can be read back from the overlay registers by initially writing the start address and then performing a sequence of RED, GREEN and BLUE reads. The address automatically incremeets to the next highest location after a BLUE read.
Internal Address Register (ADDR)
The MPU interface operates asynchronously to the pixel port. Data transfers between the color palette RAM/overlay registers and the color registers (R, G, and B as shown in the block diagram) are synchronized by internal logic, and occur in the period between MPU accesses. The MPU can be accessed at any time, even when the pixel CLOCK is stopped.
8-Bit/6-Bit Color Operation
The Command Register on the ADV473 specifies whether the MPU is reading/writing 8 bits or 6 bits of color information each cycle. For 8-bit operation, D0 is the LSB and D7 is the MSB. For 6-bit operation, color data is contained on the lower six bits of the data bus, with D0 being the LSB and D5 the MSB of color data. When writing color data, D6 and D7 are ignored. During color read cycles, D6 and D7 will be a logical "0." It should be noted that when the ADV473 is in 6-bit mode, fullscale output current will be reduced by approximately 1.5% relative to the 8-bit mode. This is the case since the 2 LSBs of each of the three DACs are always set to zero in 6-bit mode.
When accessing the color palette RAM, the address register resets to 00H following a blue read or write cycle to RAM location FFH. When accessing the overlay color registers, the address register increments following a blue read or write cycle.
REV. A
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ADV473
Command Register (CR) Color Modes
The ADV473 has an internal command register (CR). This register is 8 bits wide, CR0-CR7 and is directly mapped to the MPU data bus on the part, D0-D7. The command register can be written to or read from. It is not initialized, therefore it must be set. Figure 4 shows what each bit of the CR register controls and shows the values it must be programmed to for various modes of operation.
The ADV473 supports four color modes, 24-bit true-color, 15-bit true-color, 8-bit true-color and 8-bit pseudo-color. The mode of operation is determined by the S0 and S1 inputs, in conjunction with CR7 and CR6 of the command register. S0 and S1 are pipelined to maintain synchronization with the video data. Table III illustrates the modes of operation.
Table III. Color Operation Modes
OL3-OL0 1111 . . 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
X = Don't Care
S1, S0 XX . . XX 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11
CR7, CR6 XX . . XX 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11
Mode Overlay Color 15 . . Overlay Color 1 24-Bit True-Color 24-Bit True-Color 24-Bit True-Color Reserved 24-Bit True-Color Bypass 24-Bit True-Color Bypass 24-Bit True-Color Bypass Reserved 8-Bit Pseudo-Color (Red) 8-Bit Pseudo-Color (Green) 8-Bit Pseudo-Color (Blue) 15-Bit True-Color 8-Bit True-Color Bypass (Red) 8-Bit True-Color Bypass (Green) 8-Bit True-Color Bypass (Blue) 15-Bit True-Color Bypass
R7-R0 XXH . . XXH R7-R0 R7-R0 R7-R0 Reserved R7-R0 R7-R0 R7-R0 Reserved P7-P0 Ignored Ignored Orrrrrgg rrrgggbb Ignored Ignored Orrrrrgg
G7-G0 XXH . . XXH G7-G0 G7-G0 G7-G0 Reserved G7-G0 G7-G0 G7-G0 Reserved Ignored P7-P0 Ignored gggbbbbb Ignored rrrgggbb Ignored gggbbbbb
B7-B0 XXH . . XXH B7-B0 B7-B0 B7-B0 Reserved B7-B0 B7-B0 B7-B0 Reserved Ignored Ignored P7-P0 Ignored Ignored Ignored rrrgggbb Ignored
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
COLOR MODE SELECT
(SEE TABLE III)
CONTROL OUTPUTS PEDESTAL ENABLE CONTROL (SETUP)
CR5 0 1 0 IRE 7.5 IRE THESE BITS ARE OUTPUT ONTO THE CR3-CR0 PINS
8-BIT/6-BIT COLOR SELECT
CR4 0 1 6-BIT 8-BIT
Figure 4. Command Register (CR)
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ADV473
VIDEO MODES 24-Bit True-Color Mode 15-Bit True-Color Bypass Mode
Twenty-four bits of RGB color information may be input into the ADV473 every clock cycle. The 24 bits of pixel information are input via the R0-R7, G0-G7, and B0-B7 inputs. R0-R7 address the red color palette RAM, G0-G7 address the green color palette RAM, and B0-B7 address the blue color palette RAM. Each RAM provides 8 bits of color information to the corresponding D/A converter. The pixel read mask register is used in this mode.
24-Bit True-Color Bypass Mode
Fifteen bits of pixel information may be input into the ADV473 every clock cycle. The 15 bits of pixel information (5 bits of red, 5 bits of green, and 5 bits of blue) are input via the R0-R7 and G0-G7 inputs.
Table V. 15-Bit True-Color Video Input Format
Pixel Inputs R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0
Input Format 0 R7 R6 R5 R4 R3 G7 G6 G5 G4 G3 B7 B6 B5 B4 B3
Twenty-four bits of pixel information may be input into the ADV473 every clock cycle. The 24 bits of pixel information are input via the R0-R7, G0-G7, and B0-B7 inputs. R0-R7 drive the red DAC directly, G0-G7 drive the green DAC directly, and B0-B7 drive the blue DAC directly. The color palette RAMs and pixel read mask register are bypassed.
8-Bit Pseudo-Color Mode
Eight bits of pixel information may be input into the ADV473 every clock cycle. The 8 bits of pixel information (P0-P7) are input via the R0-R7, G0-G7 or B0-B7 inputs, as specified by CR7 and CR6. All three color palette RAMs are addressed by the same 8 bits of pixel data (P0-P7). Each RAM provides 8 bits of color information to the corresponding D/A converter. The pixel read mask register is used in this mode.
8-Bit True-Color Bypass Mode
Eight bits of pixel information may be input into the ADV473 every clock cycle. The 8 bits of pixel information are input via the R0-R7, G0-G7 or B0-B7 inputs, as specified by CR7 and CR6.
Table IV. 8-Bit True-Color Bypass Video Input Format
The 5 MSBs of the red, green, and blue DACs are driven directly by the inputs. The 3 LSBs are a logical zero. The color palette RAMs and pixel read mask register are bypassed.
15-Bit True-Color Mode
R0-R7 Inputs Selected R7 R6 R5 R4 R3 R2 R1 R0
G0-G7 Inputs Selected G7 G6 G5 G4 G3 G2 G1 G0
B0-B7 Input Selected B7 B6 B5 B4 B3 B2 B1 B0
Inputs Format R7 R6 R5 G7 G6 G5 B7 B6
Fifteen bits of pixel information may be input into the ADV473 every clock cycle. The 15 bits of pixel information are input to the device via R0-R7 and G0-G7 according to Table V. This input data points to the top 32 locations of the color palette RAM, i.e., locations 223 to 255. The 15-bit pixel input data indexes a 24-bit red, green and blue value which is clocked to the three DACs.
Overlays
The overlay inputs, OL0-OL3, have priority regardless of the color mode as shown in Table III.
Pixel Read Mask Register
As seen in the table, 3 bits of red, 3 bits of green, and 2 bits of blue data are input. The 3 MSBs of the red and green DACs are driven directly by the inputs, while the 2 MSBs of the blue DAC are driven directly. The 5 LSBs for the red and green DACs, and the 6 LSBs for the blue DAC, are a logical zero. The color palette RAMs and pixel read mask register are bypassed.
The 8-bit pixel read mask register is implemented as three 8-bit pixel read mask registers, one each for the R0-R7, G0-G7, and B0-B7 inputs. When writing to the pixel read mask register, the same data is written to all three registers. The read mask registers are located just before the color palette RAMs. Thus, they are used only in the 24-bit true-color and 8-bit pseudo-color modes since these are the only modes that use the color palette RAMs. The contents of the pixel read mask register, which may be accessed by the MPU at any time, are bit-wise logically ANDed with the 8-bit inputs prior to addressing the color palette RAMs. Bit D0 of the pixel read mask register corresponds to pixel input P0 (R0, G0, or B0 depending on the mode). Bit D0 also corresponds to data bus Bit D0.
REV. A
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ADV473
MA 26.67 V 1.000 WHITE LEVEL
92.5 IRE
9.05 7.62 0.00
0.340 7.5 IRE 0.286 40 IRE 0.000
BLACK LEVEL BLANK LEVEL SYNC LEVEL
NOTE: 75 DOUBLY TERMINATED LOAD, SETUP = 7.5 IRE, VREF = 1.235 V, R SET = 140 RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
Figure 5. Composite Video Output Waveform (Setup = 7.5 IRE)
Table VI. Video Output Truth Table (Setup = 7.5 IRE)
Description WHITE DATA DATA-SYNC BLACK BLACK-SYNC BLANK SYNC
IOUT (mA) 26.67 Data+9.05 Data+1.44 9.05 1.44 7.62 0
SYNC BLANK 1 1 0 1 0 1 0 1 1 1 1 1 0 0
DAC Input Data FFH Data Data 00H 00H XXH XXH
NOTE Typical with full-scale IOR, IOG, IOB = 26.67 mA, SETUP = 7.5 IRE, VREF = 1.235 V, RSET = 140 . External voltage reference adjusted for 26.67 mA full-scale output.
MA 25.24 V 0.950 WHITE LEVEL
100 IRE
7.62
0.286 43 IRE
BLACK/BLANK LEVEL SYNC LEVEL
0.00
0.000
NOTE: 75 DOUBLY TERMINATED LOAD, SETUP = 0 IRE, VREF = 1.235 V, R SET = 140 RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
Figure 6. Composite Video Output Waveform (Setup = 0 IRE)
Table VII. Video Output Truth Table (SETUP = 0 IRE)
Description WHITE DATA DATA-SYNC BLACK BLACK-SYNC BLANK SYNC
IOUT (mA) 25.24 Data+7.62 Data 7.62 0 7.62 0
SYNC BLANK 1 1 0 1 0 1 0 1 1 1 1 1 0 0
DAC Input Data FFH Data Data 00H 00H XXH XXH
NOTE Typical with full-scale IOR, IOG, IOB = 25.24 mA, SETUP = 0 IRE, VREF = 1.235 V, RSET = 140 . External voltage reference adjusted for 26.67 mA full-scale output.
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REV. A
ADV473
PC BOARD LAYOUT CONSIDERATIONS Digital Signal Interconnect
The layout should be optimized for lowest noise on the ADV473 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and GND pins should be minimized so as to minimize inductive ringing.
Ground Planes
The digital inputs to the ADV473 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV473 should be avoided to reduce noise pickup. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC), and not to the analog power plane.
0.1F 0.1F POWER SUPPLY DECOUPLING (0.1F CAPACITOR FOR EACH V REF GROUP) +5V (VAA ) 10F +5V (VAA) 1k (1% METAL) L1 (FERRITE BEAD) +5V (VCC ) 0.1F
The ground plane should encompass all ADV473 ground pins, current/voltage reference circuitry, power supply bypass circuitry for the ADV473, the analog output traces, and all the digital signal traces leading up to the ADV473.
Power Planes
The ADV473 and any associated analog circuitry should have its own power plane, referred to as the analog power plane. This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead, as illustrated in Figures 7 and 8. This bead should be located within three inches of the ADV473. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV473 power pins and voltage reference circuitry. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common mode.
Supply Decoupling
+5V (VAA ) 0.1F VAA COMP COMP VREFOUT VREFIN ANALOG POWER PLANE
AD589
ADV473
RSET RSET 140 IOR
(1.2 V REF )
0.1F MONITOR (CRT) 75 75
CO-AXIAL CABLE (75)
IOG 75 IOB GND 75 75 75 BNC CONNECTORS
For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Best performance is obtained with a 0.1 F ceramic capacitor decoupling each of the two groups of VAA pins to GND. These capacitors should be placed as close as possible to the device. It is important to note that while the ADV473 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and should consider using a three-terminal voltage regulator for supplying power to the analog power plane.
COMPONENT C1 - C5 C6 L1 R1, R2, R3 R4 RSET Z1
DESCRIPTION 0.1F CERAMIC CAPACITOR 10F TANTALUM CAPACITOR FERRITE BEAD 75 1% METAL FILM RESISTOR 1k 5% RESISTOR 1% METAL FILM RESISTOR 1.23V VOLTAGE REFERENCE
VENDOR PART NUMBER ERIE RPE112Z5U104M50V MALLORY CSR13G106KM FAIR-RITE 2743001111
AD589JN
Figure 7. Typical Connection Diagram (External Voltage Reference)
REV. A
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ADV473
Analog Signal Interconnect Package Thermal Considerations
The ADV473 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection. For maximum performance, the analog outputs should each have a 75 load resistor connected to GND. The connection between the current output and GND should be as close as possible to the ADV473 to minimize reflections. For more information on circuit board design and layout, see application note entitled "Design and Layout of a Video Graphics System for Reduced EMI" available from Analog Devices, Publication No. E1309-15-10/89.
0.1F 0.1F POWER SUPPLY DECOUPLING (0.1F CAPACITOR FOR EACH V REF GROUP)
In certain circumstances, the 135 MHz version of the ADV473 may require forced air cooling or the addition of a heatsink. The 68-pin PLCC has a heat resistance characteristic as shown in Table VIII.
C1761-24-1/93 PRINTED IN U.S.A.
It should be noted that information on Package Thermal Characteristics published herein may not be the most up to date at the time of reading this. Advances in packaging technology will inevitably lead to improvements in thermal data. Please contact your local sales office for the most up-to-date information.
Table VIII. Thermal Resistance vs. Airflow
Air Velocity (Linear Feet/Min) 0 (Still Air) JA (C/W) 32
50 26
100 19
200 16
+5V (VAA ) 0.1F VAA COMP COMP VREFOUT VREFIN 0.1F MONITOR (CRT) 75 75 IOG 75 IOB GND 75 75 75 BNC CONNECTORS
10 9
OUTLINE DIMENSIONS
ANALOG POWER PLANE +5V (VAA ) 10F L1 (FERRITE BEAD) +5V (VCC ) 0.1F
Dimensions shown in inches and (mm).
Plastic Leaded Chip Carrier (P-68A)
0.995 (25.27) SQ 0.885 (22.48) 61 60 PIN 1 IDENTIFIER 0.050 (1.27) TYP 0.925 (23.50) 0.895 (22.73) 0.175 (4.45) 0.169 (4.29)
ADV473
RSET RSET 140 IOR CO-AXIAL CABLE (75)
TOP VIEW
0.019 (0.48) 0.017 (0.43)
COMPONENT C1 - C5 C6 L1 R1, R2, R3 RSET
DESCRIPTION 0.1F CERAMIC CAPACITOR 10F TANTALUM CAPACITOR FERRITE BEAD 75 1% METAL FILM RESISTOR 1% METAL FILM RESISTOR
VENDOR PART NUMBER ERIE RPE112Z5U104M50V MALLORY CSR13G106KM FAIR-RITE 2743001111
26 27 0.954 (24.23) SQ 0.950 (24.13) 43 44
0.029 (0.74) 0.027 (0.69)
0.104 (2.64) TYP
Figure 8. Typical Connection Diagram (Internal Voltage Reference)
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REV. A

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